Datasheet

46.6.7 Modem Mode
The USART features the Modem mode, which enables control of the signals DTR (Data Terminal Ready), DSR (Data
Set Ready), R
TS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect), and RI (Ring Indicator). While
operating in Modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and
can detect level change on DSR, DCD, CTS, and RI.
Modem mode is enabled by writing the value 0x3 to US_MR.USART_MODE. While operating in Modem mode, the
USART behaves as though in Asynchronous mode and all the parameter configurations are available.
The following table provides the correspondence of the USART signals with modem connection standards.
Table 46-11. Circuit References
USART Pin V24 CCITT Direction
TXD 2 103 From terminal to modem
RTS 4 105 From terminal to modem
DTR 20 108.2 From terminal to modem
RXD 3 104 From modem to terminal
CTS 5 106 From terminal to modem
DSR 6 107 From terminal to modem
DCD 8 109 From terminal to modem
RI 22 125 From terminal to modem
The control of the DTR output pin is performed by writing a ‘1’ to US_CR.DTRDIS and US_CR.DTREN. The disable
command forces the corresponding pin to its inactive level, i.e., high. The enable command forces the corresponding
pin to its active level, i.e., low
. The RTS output pin is automatically controlled in this mode.
The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the bits RIIC,
DSRIC, DCDIC and CTSIC in US_CSR are set and can trigger an interrupt. The status is automatically cleared when
US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state.
If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter
is actually disabled.
46.6.8 SPI Mode
The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with
external devices in Master or Slave mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs. During a data transfer,
one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which have
data shifted into and out by the master. Different CPUs can take turns being masters and one master may
simultaneously shift data into multiple slaves. (Multiple master protocol is the opposite of single master protocol,
where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can
address only one SPI slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the
slave.
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
• Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master
may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
• Slave Select (NSS): This control line allows the master to select or deselect the slave.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1204