Datasheet

46.6.3.8 Parity
The USART supports five Parity modes. The PAR field also enables Multidrop mode, see “Multidrop Mode”. Even and
odd parity bit generation and error detection are supported. The configuration is done in US_MR.P
AR.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the
character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is
selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is
even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s
and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator
of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error if the parity
bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all
characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
The following table shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the
configuration of the USART. Because there are two bits set to 1 in the character value, the parity bit is set to ‘1’ when
the parity is odd, or configured to ‘0’ when the parity is even.
Table 46-6. Parity Bit Examples
Character Hexadecimal Binary Parity Bit Parity Mode
A 0x41 0100 0001 1 Odd
A 0x41 0100 0001 0 Even
A 0x41 0100 0001 1 Mark
A 0x41 0100 0001 0 Space
A 0x41 0100 0001 None None
When the receiver detects a parity error, it sets US_CSR.PARE (Parity Error). PARE can be cleared by writing a ‘1’ to
the RSTST
A bit the US_CR. The following figure illustrates the parity bit status setting and clearing.
Figure 46-21. Parity Error
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit
Bad
Parity
Bit
Stop
Bit
B
aud Rate
Clock
Write
US_CR
PARE
RXRDY
RSTSTA = 1
Parity Error
Detect
Time
Flags
Report
Time
46.6.3.9 Multidrop Mode
If the value 0x6 or 0x07 is written to US_MR.PAR, the USART runs in Multidrop mode. This mode differentiates the
data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted
with the parity bit at 1.
If the USAR
T is configured in Multidrop mode, the receiver sets PARE when the parity bit is high and the transmitter
is able to send a character with the parity bit high when a ‘1’ is written to US_CR.SENTA.
To handle parity error, PARE is cleared when a ‘1’ is written to US_CR.RSTSTA.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1194