Datasheet

Figure 46-11. Asynchronous Start Detection
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 0
1 2 3 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D0
Sampling
Figure 46-12. Asynchronous Character Reception
D0
D1
D2
D3
D4
D5 D6 D7
RXD
Parity
Bit
Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
46.6.3.4 Manchester Decoder
When US_MR.MAN is ‘1’, the Manchester decoder is enabled. The decoder performs both preamble and start frame
delimiter detection. One input line is dedicated to Manchester encoded input data.
An optional preamble sequence can be defined, and its length is user-defined and totally independent of the emitter
side. The length of the preamble sequence is configured using US_MAN.RX_PL. If RX_PL is ‘0’, no preamble is
detected and the function is disabled. The polarity of the input stream is configured with US_MAN.RX_MPOL.
Depending on the desired application, the preamble pattern matching is to be defined via the US_MAN. See Figure
46-8 for available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder
. If US_MR.ONEBIT
is written to ‘1’, only a zero-encoded Manchester can be detected as a valid start frame delimiter. If US_MR.ONEBIT
is written to ‘0’, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting
transition on incoming stream. If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See
Figure 46-13. The sample pulse rejection mechanism applies.
The US_MAN.RXIDLEV informs the USART of the receiver line idle state value (receiver line inactive). The user
must define RXIDLEV to ensure reliable synchronization. By default, RXIDLEV is set to ‘1’ (receiver line is at level 1
when there is no activity).
Figure 46-13. Asynchronous Start Bit Detection
Manchester
Encoded
Data
TXD
1 2 3 4
Sampling
Clock
(16X)
Start
Detection
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1190