Datasheet

Figure 46-2. Baud Rate Generator
Peripheral clock/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
PMC.PCKx
Peripheral clock
USCLKS
OVER
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
SCK
(CLKO = 1)
SCK
(CLKO = 0)
Selected Clock
Selected
Clock
46.6.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in Asynchronous mode, the selected clock is first divided by the value of
US_BRGR.CD. The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the value of US_MR.OVER.
If OVER is set to ‘1’, the receiver sampling is eight times higher than the baud rate clock. If OVER is set to ‘0’, the
sampling is performed at 16 times the baud rate clock.
The baud rate is calculated as per the following formula:
BaudRate =
SelectedClock
8 2  OVER CD
This gives a maximum baud rate of peripheral clock divided by 8, assuming that the peripheral clock is the highest
possible clock and that the OVER is written to ‘1’.
46.6.1.1.1 Baud Rate Calculation Example
The following table shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock
frequencies. This table also shows the actual resulting baud rate and the error
.
Table 46-2. Baud Rate Example (OVER = 0)
Source Clock
(MHz)
Expected Baud Rate
(bit/s)
Calculation Result CD Actual Baud Rate
(bit/s)
Error
3,686,400 38,400 6.00 6 38,400.00 0.00%
4,915,200 38,400 8.00 8 38,400.00 0.00%
5,000,000 38,400 8.14 8 39,062.50 1.70%
7,372,800 38,400 12.00 12 38,400.00 0.00%
8,000,000 38,400 13.02 13 38,461.54 0.16%
12,000,000 38,400 19.53 20 37,500.00 2.40%
12,288,000 38,400 20.00 20 38,400.00 0.00%
14,318,180 38,400 23.30 23 38,908.10 1.31%
14,745,600 38,400 24.00 24 38,400.00 0.00%
18,432,000 38,400 30.00 30 38,400.00 0.00%
24,000,000 38,400 39.06 39 38,461.54 0.16%
24,576,000 38,400 40.00 40 38,400.00 0.00%
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1183