Datasheet

46. Universal Synchronous Asynchronous Receiver Transceiver (USART)
46.1 Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity
, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error
detection. The receiver timeout enables handling variable-length frames and the transmitter timeguard facilitates
communications with slow remote devices. Multidrop communications are also supported through address bit
handling in reception and transmission.
The USART features three test modes: Remote Loopback, Local Loopback and Automatic Echo.
The USART supports specific operating modes providing interfaces on RS485, LIN, LON, and SPI buses, with
ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware
handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the DMA Controller, which enables data transfers to the transmitter and from
the receiver. The DMAC provides chained buffer management without any intervention of the processor.
46.2 Embedded Characteristics
• Programmable Baud Rate Generator
• 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
– 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
– Parity Generation and Error Detection
– Framing Error Detection, Overrun Error Detection
– Digital Filter on Receive Line
– MSB- or LSB-first
– Optional Break Generation and Detection
– By 8 or by 16 Oversampling Receiver Frequency
– Optional Hardware Handshaking RTS-CTS
– Optional Modem Signal Management DTR-DSR-DCD-RI
– Receiver Timeout and Transmitter Timeguard
– Optional Multidrop Mode with Address Generation and Detection
• RS485 with Driver Control Signal
• ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
– NACK Handling, Error Counter with Repetition and Iteration Limit
• IrDA Modulation and Demodulation
– Communication at up to 115.2 kbit/s
• SPI Mode
– Master or Slave
– Serial Clock Programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to f
peripheral clock
/6
• LIN Mode
– Compliant with LIN 1.3 and LIN 2.0 SPECIFICATIONS
– Master or Slave
– Processing of Frames with Up to 256 Data Bytes
– Response Data Length can be Configurable or Defined Automatically by the Identifier
– Self-synchronization in Slave Node Configuration
– Automatic Processing and Verification of the “Synch Break” and the “Synch Field”
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1179