Datasheet

Value Description
0
This bit is cleared when the corresponding bit in I2SC_SCR is written to ’1’.
1
This bit is set when an overrun error occurs on I2SC_RHR or when the corresponding bit in I2SC_SSR
is written to ’1’.
Bit 1 – RXRDY Receive Ready
Value Description
0
This bit is cleared when I2SC_RHR is read.
1
This bit is set when received data is present in I2SC_RHR.
Bit 0 – RXEN Receiver Enabled
Value Description
0
This bit is cleared when the receiver is disabled, following a RXDIS or SWRST request in I2SC_CR.
1
This bit is set when the receiver is enabled, following a RXEN request in I2SC_CR.
SAM E70/S70/V70/V71 Family
Inter-IC Sound Controller (I2SC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1171