Datasheet

45.8.3 I2SC Status Register
Name: I2SC_SR
Offset: 0x08
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
TXURCH[1:0]
Access
R R
Reset 0 0
Bit 15 14 13 12 11 10 9 8
RXORCH[1:0]
Access
R R
Reset 0 0
Bit 7 6 5 4 3 2 1 0
TXUR TXRDY TXEN RXOR RXRDY RXEN
Access
R R R R R R
Reset 0 0 0 0 0 0
Bits 21:20 – TXURCH[1:0] T
ransmit Underrun Channel
Value Description
0
This field is cleared when I2SC_SCR.TXUR is written to ’1’.
1
Bit i of this field is set when a transmit underrun error occurred in channel i (i = 0 for first channel of the
frame).
Bits 9:8 – RXORCH[1:0] Receive Overrun Channel
This field is cleared when I2SC_SCR.RXOR is written to ’1’.
Bit i of this field is set when a receive overrun error occurred in channel i (i = 0 for first channel of the frame).
Bit 6 – TXUR T
ransmit Underrun
Value Description
0
This bit is cleared when the corresponding bit in I2SC_SCR is written to ’1’.
1
This bit is set when an underrun error occurs on I2SC_THR or when the corresponding bit in
I2SC_SSR is written to ’1’.
Bit 5 – TXRDY T
ransmit Ready
Value Description
0
This bit is cleared when data is written to I2SC_THR.
1
This bit is set when I2SC_THR is empty and can be written with new data to be transmitted.
Bit 4 – TXEN T
ransmitter Enabled
Value Description
0
This bit is cleared when the transmitter is disabled, following a I2SC_CR.TXDIS or I2SC_CR.SWRST
request.
1
This bit is set when the transmitter is enabled, following a I2SC_CR.TXEN request.
Bit 2 – RXOR Receive Overrun
SAM E70/S70/V70/V71 Family
Inter-IC Sound Controller (I2SC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1170