Datasheet

45.8.2 I2SC Mode Register
Name: I2SC_MR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write
The I2SC_MR must be written when the I2SC is stopped. The proper sequence is to write to I2SC_MR, then write to
I2SC_CR to enable the I2SC or to disable the I2SC before writing a new value to I2SC_MR.
Bit 31 30 29 28 27 26 25 24
IWS IMCKMODE IMCKFS[5:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
IMCKDIV[5:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TXSAME TXDMA TXMONO RXLOOP RXDMA RXMONO
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATALENGTH[2:0] MODE
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 31 – IWS I2SC_WS Slot Width
Refer to table Slot Length (I2S format).
Value Description
0
I2SC_WS slot is 32 bits wide for DATALENGTH = 18/20/24 bits.
1
I2SC_WS slot is 24 bits wide for DATALENGTH = 18/20/24 bits.
Bit 30 – IMCKMODE Master Clock Mode
If I2S
C_MCK frequency is the same as I2SC_CK, IMCKMODE must be cleared. Refer to section Serial Clock and
Word Select Generation and table Slot Length.
Value Description
0
No master clock generated (Selected Clock drives I2SC_CK output).
1
Master clock generated (internally generated clock is used as I2SC_MCK output).
Bits 29:24 – IMCKFS[5:0] Master Clock to f
s
Ratio
Master clock frequency is [2 x 16 × (IMCKFS + 1)]
/ (IMCKDIV + 1) times the sample rate, i.e., I2SC_WS frequency.
Value Name Description
0
M2SF32 Sample frequency ratio set to 32
1
M2SF64 Sample frequency ratio set to 64
2
M2SF96 Sample frequency ratio set to 96
3
M2SF128 Sample frequency ratio set to 128
5
M2SF192 Sample frequency ratio set to 192
7
M2SF256 Sample frequency ratio set to 256
11
M2SF384 Sample frequency ratio set to 384
15
M2SF512 Sample frequency ratio set to 512
23
M2SF768 Sample frequency ratio set to 768
31
M2SF1024 Sample frequency ratio set to 1024
SAM E70/S70/V70/V71 Family
Inter-IC Sound Controller (I2SC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1167