Datasheet

45.6.8 DMA Controller Operation
All receiver audio channels can be assigned to a single DMA Controller channel or individual audio channels can be
assigned to one DMA Controller
channel per audio channel. The same channel assignment choice applies to the
transmitter audio channels.
Channel assignment is selected by writing to the I2SC_MR.RXDMA and I2SC_MR.TXDMA bits. If a single DMA
Controller channel is selected, all data samples use I2SC receiver or transmitter DMA Controller channel 0.
The DMA Controller reads from the I2SC_RHR and writes to the I2SC_THR for both audio channels successively.
The DMA Controller transfers may use 32-bit word, 16-bit halfword, or 8-bit byte depending on the value of the
I2SC_MR.DATALENGTH field.
45.6.9 Loopback Mode
For debug purposes, the I2SC can be configured to loop back the transmitter to the Receiver. Writing a ’1’ to the
I2SC_MR.LOOP bit internally connects I2S
C_DO to I2SC_DI, so that the transmitted data is also received. Writing
a ’0’ to I2SC_MR.LOOP restores the normal behavior with independent Receiver and Transmitter. As for other
changes to the Receiver or Transmitter configuration, the I2SC Receiver and Transmitter must be disabled before
writing to I2SC_MR to update I2SC_MR.LOOP.
45.6.10 Interrupts
An I2SC interrupt request can be triggered whenever one or several of the following bits are set in I2SC_SR: Receive
Ready (RXRDY), Receive Overrun (RXOR), Transmit Ready (TXRDY) or Transmit Underrun (TXUR).
The interrupt request is generated if the corresponding bit in the Interrupt Mask Register (I2SC_IMR) is set. Bits in
I2SC_IMR are set by writing a ’1’ to the corresponding bit in I2SC_IER and cleared by writing a ’1’ to the
corresponding bit in the Interrupt Disable Register (I2SC_IDR). The interrupt request remains active until the
corresponding bit in I2SC_SR is cleared by writing a ’1’ to the corresponding bit in the Status Clear Register
(I2SC_SCR).
For debug purposes, interrupt requests can be simulated by writing a ’1’ to the corresponding bit in the Status Set
Register (I2SC_SSR).
Figure 45-4. Interrupt Block Diagram
I2SC_IER
TXRDY
TXUR
RXRDY
RXOR
Set Clear
I2SC interrupt line
I2SC_IDRI2SC_IMR
Transmitter
Receiver
Interrupt
Logic
45.7 I2SC Application Examples
The I2SC supports several serial communication modes used in audio or high-speed serial links. Examples of
standard applications are shown in the following figures. All serial link applications supported by the I2SC are not
listed here.
SAM E70/S70/V70/V71 Family
Inter-IC Sound Controller (I2SC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1160