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19. Bus Matrix (MA
TRIX)
45.6.4 I
2
S Reception and T
ransmission Sequence
As specified in the I
2
S protocol, data bits are left-justified in the word select time slot, with the MSB transmitted first,
starting one clock period after the transition on the word select line.
Figure 45-2. I
2
S Reception and T
ransmission Sequence
Serial Clock
I2SCK
Word Select
I2SWS
Data
I2SDI/I2SDO
MSB MSBLSB
Left Channel Right Channel
Serial Clock
I2SC_CK
Word Select
I2SC_WS
Data
I2SC_DI/I2SC_DO
MSB MSBLSB
Left Channel Right Channel
Data bits are sent on the falling edge of the serial clock and sampled on the rising edge of the serial clock. The word
select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the
I2SC_MR.DA
TALENGTH field.
If the time slot allows for more data bits than written in the I2SC_MR.DATALENGTH field, zeroes are appended to the
transmitted data word or extra received bits are discarded.
45.6.5 Serial Clock and Word Select Generation
The generation of clocks in the I2SC is described in figure ”Mono”.
In Slave mode, the serial clock and word select clock are driven by an external master. I2SC_CK and I2SC_WS pins
are inputs.
In Master mode, the user can configure the master clock, serial clock, and word select clock through the I2SC_MR.
I2SC_MCK, I2SC_CK, and I2SC_WS pins are outputs and MCK is used to derive the I2SC clocks.
In Master mode, if the peripheral clock frequency is higher than 96 MHz, the GCLK[PID] from PMC must be selected
as I2SC input clock by writing a ‘1’ in the I2SCxCC bit of the CCFG_PCCR register. Refer to the section “Bus Matrix
(MATRIX)” for more details.
Audio codecs connected to the I2SC pins may require a master clock (I2SC_MCK) signal with a frequency multiple of
the audio sample frequency (f
s
), such as 256f
s
. When the I2SC is in Master mode, writing a ’1’ to
I2SC_MR.IMCKMODE outputs MCK as master clock to the I2SC_MCK pin, and divides MCK to create the internal bit
clock, output on the I2SC_CK pin. The clock division factor is defined by writing to I2SC_MR.IMCKFS and
I2SC_MR.DATALENGTH, as described in the I2SC_MR.IMCKFS field description.
The master clock (I2SC_MCK) frequency is (2×16 × (IMCKFS + 1)) / (IMCKDIV + 1) times the sample frequency (f
s
),
i.e., I2SC_WS frequency.
SAM E70/S70/V70/V71 Family
Inter-IC Sound Controller (I2SC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1157