Datasheet

44.9.16 SSC Interrupt Mask Register
Name: SSC_IMR
Offset: 0x4C
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
RXSYN TXSYN CP1 CP0
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OVRUN RXRDY TXEMPTY TXRDY
Access
R R R R
Reset 0 0 0 0
Bit 11 – RXSYN Rx Sync Interrupt Mask
Value Description
0
The Rx Sync Interrupt is disabled.
1
The Rx Sync Interrupt is enabled.
Bit 10 – TXSYN Tx Sync Interrupt Mask
Value Description
0
The Tx Sync Interrupt is disabled.
1
The Tx Sync Interrupt is enabled.
Bit 9 – CP1 Compare 1 Interrupt Mask
Value Description
0
The Compare 1 Interrupt is disabled.
1
The Compare 1 Interrupt is enabled.
Bit 8 – CP0 Compare 0 Interrupt Mask
Value Description
0
The Compare 0 Interrupt is disabled.
1
The Compare 0 Interrupt is enabled.
Bit 5 – OVRUN Receive Overrun Interrupt Mask
Value Description
0
The Receive Overrun Interrupt is disabled.
1
The Receive Overrun Interrupt is enabled.
Bit 4 – RXRDY Receive Ready Interrupt Mask
Value Description
0
The Receive Ready Interrupt is disabled.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1150