Datasheet

44.9.14 SSC Interrupt Enable Register
Name: SSC_IER
Offset: 0x44
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
RXSYN TXSYN CP1 CP0
Access
W W W W
Reset – – – –
Bit 7 6 5 4 3 2 1 0
OVRUN RXRDY TXEMPTY TXRDY
Access
W W W W
Reset – – – –
Bit 11 – RXSYN Rx Sync Interrupt Enable
Value Description
0
No effect.
1
Enables the Rx Sync Interrupt.
Bit 10 – TXSYN Tx Sync Interrupt Enable
Value Description
0
No effect.
1
Enables the Tx Sync Interrupt.
Bit 9 – CP1 Compare 1 Interrupt Enable
Value Description
0
No effect.
1
Enables the Compare 1 Interrupt.
Bit 8 – CP0 Compare 0 Interrupt Enable
Value Description
0
No effect.
1
Enables the Compare 0 Interrupt.
Bit 5 – OVRUN Receive Overrun Interrupt Enable
Value Description
0
No effect.
1
Enables the Receive Overrun Interrupt.
Bit 4 – RXRDY Receive Ready Interrupt Enable
Value Description
0
No effect.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1146