Datasheet

44.9.13 SSC Status Register
Name: SSC_SR
Offset: 0x40
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RXEN TXEN
Access
R R
Reset 0 0
Bit 15 14 13 12 11 10 9 8
RXSYN TXSYN CP1 CP0
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OVRUN RXRDY TXEMPTY TXRDY
Access
R R R R
Reset 0 0 0 0
Bit 17 – RXEN Receive Enable
Value Description
0
Receive is disabled.
1
Receive is enabled.
Bit 16 – TXEN T
ransmit Enable
Value Description
0
Transmit is disabled.
1
Transmit is enabled.
Bit 11 – RXSYN Receive Sync
Value Description
0
An Rx Sync has not occurred since the last read of the Status Register.
1
An Rx Sync has occurred since the last read of the Status Register.
Bit 10 – TXSYN T
ransmit Sync
Value Description
0
A Tx Sync has not occurred since the last read of the Status Register.
1
A Tx Sync has occurred since the last read of the Status Register.
Bit 9 – CP1 Compare 1
Value Description
0
A compare 1 has not occurred since the last read of the Status Register.
1
A compare 1 has occurred since the last read of the Status Register.
Bit 8 – CP0 Compare 0
Value Description
0
A compare 0 has not occurred since the last read of the Status Register.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1144