Datasheet

44.9.6 SSC Transmit Frame Mode Register
Name: SSC_TFMR
Offset: 0x1C
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
FSLEN_EXT[3:0] FSEDGE
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
FSDEN FSOS[2:0] FSLEN[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATNB[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MSBF DATDEF DATLEN[4:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 31:28 – FSLEN_EXT[3:0] FSLEN Field Extension
Extends FSLEN field. For details, seee FSLEN bit description below
.
Bit 24 – FSEDGE Frame Sync Edge Detection
Determines which edge on frame synchronization will generate the interrupt TXSYN (Status Register).
Value Name Description
0
POSITIVE Positive Edge Detection
1
NEGATIVE Negative Edge Detection
Bit 23 – FSDEN Frame Sync Data Enable
Value Description
0
The TD line is driven with the default value during the Transmit Frame Sync signal.
1
SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
Bits 22:20 – FSOS[2:0] T
ransmit Frame Sync Output Selection
Value Name Description
0
NONE None, TF pin is an input
1
NEGATIVE Negative Pulse, TF pin is an output
2
POSITIVE Positive Pulse, TF pin is an output
3
LOW Driven Low during data transfer
4
HIGH Driven High during data transfer
5
TOGGLING Toggling at each start of data transfer
Bits 19:16 – FSLEN[3:0] T
ransmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from SSC_TSHR if
FSDEN is 1.
This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Transmit Clock period.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1136