Datasheet

44.9.4 SSC Receive Frame Mode Register
Name: SSC_RFMR
Offset: 0x14
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
FSLEN_EXT[3:0] FSEDGE
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
FSOS[2:0] FSLEN[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATNB[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MSBF LOOP DATLEN[4:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 31:28 – FSLEN_EXT[3:0] FSLEN Field Extension
Extends FSLEN field. For details, see FSLEN: Receive Frame Sync Length.
Bit 24 – FSEDGE Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register
.
Value Name Description
0
POSITIVE Positive Edge Detection
1
NEGATIVE Negative Edge Detection
Bits 22:20 – FSOS[2:0] Receive Frame Sync Output Selection
Value Name Description
0
NONE None, RF pin is an input
1
NEGATIVE Negative Pulse, RF pin is an output
2
POSITIVE Positive Pulse, RF pin is an output
3
LOW Driven Low during data transfer, RF pin is an output
4
HIGH Driven High during data transfer, RF pin is an output
5
TOGGLING Toggling at each start of data transfer, RF pin is an output
Bits 19:16 – FSLEN[3:0] Receive Frame Sync Length
This field defines the number of bits sampled and stored in the Receive Sync Data Register
. When this mode is
selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to
be compared to the Compare 0 or Compare 1 register.
This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Receive Clock periods.
Bits 11:8 – DATNB[3:0] Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1132