Datasheet

Value Name Description
8
CMP_0 Compare 0
Bits 7:6 – CKG[1:0] Receive Clock Gating Selection
Value Name Description
0
CONTINUOUS None
1
EN_RF_LOW Receive Clock enabled only if RF Low
2
EN_RF_HIGH Receive Clock enabled only if RF High
Bit 5 – CKI Receive Clock Inversion
CKI af
fects only the Receive Clock and not the output clock signal.
Value Description
0
The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame
Sync signal output is shifted out on Receive Clock rising edge.
1
The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame
Sync signal output is shifted out on Receive Clock falling edge.
Bits 4:2 – CKO[2:0] Receive Clock Output Mode Selection
Value Name Description
0
NONE None, RK pin is an input
1
CONTINUOUS Continuous Receive Clock, RK pin is an output
2
TRANSFER Receive Clock only during data transfers, RK pin is an output
Bits 1:0 – CKS[1:0] Receive Clock Selection
Value Name Description
0
MCK Divided Clock
1
TK TK Clock signal
2
RK RK pin
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1131