Datasheet

44.9.2 SSC Clock Mode Register
Name: SSC_CMR
Offset: 0x4
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
DIV[11:8]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIV[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 11:0 – DIV[11:0] Clock Divider
Value Description
0
The Clock Divider is not active.
Any
other
value
The divided clock equals the peripheral clock divided by 2 times DIV.
The maximum bit rate is f
peripheral clock
/2. The minimum bit rate is f
peripheral clock
/2 × 4095 = f
peripheral clock
/
8190.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1129