Datasheet

44.9.1 SSC Control Register
Name: SSC_CR
Offset: 0x0
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
SWRST TXDIS TXEN
Access
W W W
Reset – – –
Bit 7 6 5 4 3 2 1 0
RXDIS RXEN
Access
W W
Reset – –
Bit 15 – SWRST Software Reset
Value Description
0
No effect.
1
Performs a software reset. Has priority on any other bit in SSC_CR.
Bit 9 – TXDIS T
ransmit Disable
Value Description
0
No effect.
1
Disables Transmit. If a character is currently being transmitted, disables at end of current character
transmission.
Bit 8 – TXEN T
ransmit Enable
Value Description
0
No effect.
1
Enables Transmit if TXDIS is not set.
Bit 1 – RXDIS Receive Disable
Value Description
0
No effect.
1
Disables Receive. If a character is currently being received, disables at end of current character
reception.
Bit 0 – RXEN Receive Enable
Value Description
0
No effect.
1
Enables Receive if RXDIS is not set.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1128