Datasheet

Figure 44-18. Receive Frame Format in Continuous Mode (STTDLY = 0)
Data
Data
Start = Enable Receiver
To SSC_RHR
To SSC_RHR
RD
DATLEN
DATLEN
44.8.8 Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop
Mode (LOOP) bit in the SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is
connected to TK.
44.8.9 Interrupt
Most bits in the SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing
the Interrupt Enable Register (SSC_IER) and Interrupt Disable Register (SSC_IDR). These registers enable and
disable, respectively
, the corresponding interrupt by setting and clearing the corresponding bit in the Interrupt Mask
Register (SSC_IMR), which controls the generation of interrupts by asserting the SSC interrupt line connected to the
interrupt controller.
Figure 44-19. Interrupt Block Diagram
SSC_IMR
Interrupt
Control
SSC Interrupt
Set
RXRDY
OVRUN
RXSYN
Receiver
Transmitter
TXRDY
TXEMPTY
TXSYN
Clear
SSC_IER
SSC_IDR
44.8.10 Register Write Protection
To prevent any single software error from corrupting SSC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the SSC W
rite Protection Mode Register (SSC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SSC Write Protection Status Register
(SSC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the SSC_WPSR.
The following registers can be write-protected:
• SSC Clock Mode Register
• SSC Receive Clock Mode Register
• SSC Receive Frame Mode Register
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1124