Datasheet

During the Frame Sync signal, the receiver can sample the RD line and store the data in the Receive Sync Holding
Register and the transmitter can transfer T
ransmit Sync Holding Register in the shift register. The data length to be
sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR
and has a maximum value of 256.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay
between the start event and the current data reception, the data sampling operation is performed in the Receive Sync
Holding Register through the receive shift register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN)
in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the
current data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding
Register is transferred in the Transmit Register, then shifted out.
44.8.5.2 Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the
corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on Frame Sync Edge detection (signals
RF/TF).
44.8.6 Receive Compare Modes
Figure 44-15. Receive Compare Modes
CMP0
CMP3
CMP2
CMP1
Ignored
B0
B2
B1
Start
RK
RD
(Input)
FSLEN
STTDLY
DATLEN
44.8.6.1 Compare Functions
The length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is
defined by FSLEN, but with a maximum value of 256 bits. Comparison is always done by comparing the last bits
received with the comparison pattern. Compare 0 can be one start event of the receiver
. In this case, the receiver
compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register
(SSC_RC0R). When this start event is selected, the user can program the receiver to start a new data transfer either
by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the
STOP bit in the SSC_RCMR.
44.8.7 Data Format
The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame
Mode Register (SSC_TFMR) and the Receive Frame Mode Register (SSC_RFMR). In either case, the user can
independently select the following parameters:
• Event that starts the data transfer (START)
• Delay in number of bit periods between the start event and the first data bit (STTDLY)
• Length of the data (DATLEN)
• Number of data to be transferred for each start event (DATNB)
• Length of synchronization transferred for each start event (FSLEN)
• Bit sense: most or least significant bit first (MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while
not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data
Default Value (DATDEF) bits in SSC_TFMR.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1122