Datasheet

19.4.10 SMC NAND Flash Chip Select Configuration Register
Name: CCFG_SMCNFCS
Offset: 0x0124
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
SDRAMEN SMC_NFCS3 SMC_NFCS2 SMC_NFCS1 SMC_NFCS0
Access
Reset 0 0 0 0 0
Bit 4 – SDRAMEN SDRAM Enable
WARNING
This bit must not be used if SMC_NFCS1 is set.
WARNING: This must not be used if SMC_NFCS1 is set.
Value Description
0
NCS1 is not assigned to SDRAM.
1
NCS1 is assigned to SDRAM.
Bit 3 – SMC_NFCS3 SMC NAND Flash Chip Select 3 Assignment
Value Description
0
NCS3 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS3).
1
NCS3 is assigned to a NAND Flash (NANDOE and NANWE used for NCS3).
Bit 2 – SMC_NFCS2 SMC NAND Flash Chip Select 2 Assignment
Value Description
0
NCS2 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS2).
1
NCS2 is assigned to a NAND Flash (NANDOE and NANWE used for NCS2).
Bit 1 – SMC_NFCS1 SMC NAND Flash Chip Select 1 Assignment
WARNING
This bit must not be used if SDRAMEN is set.
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 112