Datasheet

• Peripheral clock divided by 2 if Receive Frame Synchronization is input
•
Peripheral clock divided by 3 if Receive Frame Synchronization is output
In addition, the maximum clock speed allowed on the TK pin is:
• Peripheral clock divided by 6 if Transmit Frame Synchronization is input
• Peripheral clock divided by 2 if Transmit Frame Synchronization is output
These are only theoretical speed limits for first order calculations. Exact speed limits on TK and RK are provided in
the "Electrical Characteristics" chapter.
44.8.2 Transmit Operations
A transmit frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured by setting the SSC_TCMR. See Start.
The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See Frame
Synchronization.
To transmit data, the transmitter uses a shift register clocked by the transmit clock signal and the start mode selected
in the SSC_TCMR. Data is written by the application to the SSC_THR then transferred to the shift register according
to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in the SSC_SR.
When the Transmit Holding register is transferred in the transmit shift register, the status flag TXRDY is set in the
SSC_SR and additional data can be loaded in the holding register.
Figure 44-11. Transmit Block Diagram
Transmit Shift Register
TD
SSC_TFMR.FSLENSSC_TFMR.DATLEN
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.DATDEF
SSC_TFMR.MSBF
SSC_TCMR.STTDLY != 0
SSC_TFMR.FSDEN
10
TX Controller
SSC_TCMR.START
RF
Start
Selector
TXEN
RX Start
TXEN
RF
Start
Selector
RXEN
RC0R
TX Start
TX Start
Transmit Clock
TX Controller counter reached STTDLY
SSC_RCMR.START
SSC_THR
SSC_TSHR
SSC_CRTXEN
SSC_SRTXEN
SSC_CRTXDIS
44.8.3 Receive Operations
A receive frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See Start.
The frame synchronization is configured by setting the Receive Frame Mode Register (SSC_RFMR). See Frame
Synchronization.
The receiver uses a shift register clocked by the receive clock signal and the start mode selected in the SSC_RCMR.
The data is transferred from the shift register depending on the data format selected.
When the receiver shift register is full, the SSC transfers this data in the holding register
, the status flag RXRDY is set
in the SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1119