Datasheet

44.8.1 Clock Management
The transmit clock can be generated by:
•
an external clock received on the TK I/O pad
• the receive clock
• the internal clock divider
The receive clock can be generated by:
• an external clock received on the RK I/O pad
• the transmit clock
• the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receive block can
generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave mode data transfers.
44.8.1.1 Clock Divider
Figure 44-7. Divided Clock Block Diagram
Peripheral Clock
Divided Clock
Clock Divider
/ 2
12-bit Counter
SSC_CMR
The peripheral clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is
4095) in the Clock Mode Register (SSC_CMR), allowing a peripheral clock division by up to 8190. The Divided Clock
is provided to both the receiver and the transmitter
. When this field is programmed to 0, the Clock Divider is not used
and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of peripheral clock divided
by 2 times DIV. Each level of the Divided Clock has a duration of the peripheral clock multiplied by DIV. This ensures
a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.
Figure 44-8. Divided Clock Generation
Peripheral Clock
Divided Clock
DIV = 1
Peripheral Clock
Divided Clock
DIV = 3
Divided Clock Frequency = f
peripheral clock
/2
Divided Clock Frequency = f
peripheral clock
/6
44.8.1.2 Transmit Clock Management
The transmit clock is generated from the receive clock or the divider clock or an external clock scanned on the TK I/O
pad. The transmit clock is selected by the CKS field in the T
ransmit Clock Mode Register (SSC_TCMR). Transmit
Clock can be inverted independently by the CKI bits in the SSC_TCMR.
The transmitter can also drive the TK I/O pad continuously or be limited to the current data transfer. The clock output
is configured by the SSC_TCMR. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the SSC_TCMR to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO
field) can lead to unpredictable results.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1117