Datasheet

Figure 44-5. Time Slot Application Block Diagram
SSC
RK
RF
RD
TD
TF
TK
SCLK
FSYNC
Data Out
Data In
CODEC
First
Time Slot
Serial Data Clock (SCLK)
Frame Sync (FSYNC)
Serial Data Out
Serial Data in
CODEC
Second
Time Slot
First Time Slot
Second Time Slot
Dstart
Dend
44.6 Pin Name List
Table 44-1. I/O Lines Description
Pin Name Pin Description Type
RF Receive Frame Synchronization Input/Output
RK Receive Clock Input/Output
RD Receive Data Input
TF Transmit Frame Synchronization Input/Output
TK Transmit Clock Input/Output
TD Transmit Data Output
44.7 Product Dependencies
44.7.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver
, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the
SSC Peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to
the SSC Peripheral mode.
SAM E70/S70/V70/V71 Family
Synchronous Serial Controller (SSC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1115