Datasheet

19.4.9 Dynamic Clock Gating Register
Name: CCFG_DYNCKG
Offset: 0x011C
Reset: 0
Property: Read/Write
Note: Clearing this register optimizes the power consumption of the system bus circuitry
.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
EFCCKG BRIDCKG MATCKG
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – EFCCKG EFC Dynamic Clock Gating Enable
Value Description
0
EFC dynamic clock gating enabled. The Embedded Flash Controller circuitry is driven by the clock only
when an access to the Flash memory is being performed. Power consumption is optimized.
1
EFC dynamic clock gating disabled. The Embedded Flash Controller is always driven by the clock in
Active mode.
Bit 1 – BRIDCKG Bridge Dynamic Clock Gating Enable
Value Description
0
Bridge dynamic clock gating enabled. The peripheral bridge circuitry is driven by the clock only when a
transfer to/from any peripheral located on the APB bus is being performed. Power consumption is
optimized.
1
Bridge dynamic clock gating disabled. The peripheral bridge circuitry is always driven by the clock in
Active mode.
Bit 0 – MATCKG MA
TRIX Dynamic Clock Gating
Value Description
0
MATRIX dynamic clock gating enabled. The MATRIX circuitry is driven by the clock only when a
transfer to a peripheral is being performed. Power consumption is optimized.
1
MATRIX dynamic clock gating disabled. The MATRIX circuitry is always driven by the clock in Active
mode.
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 111