Datasheet

43.7.11 TWIHS Interrupt Mask Register
Name: TWIHS_IMR
Offset: 0x2C
Reset: 0x00000000
Property: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SMBHHM SMBDAM PECERR TOUT MCACK
Access
R R R R R
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
EOSACC SCL_WS ARBLST NACK
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
UNRE OVRE GACC SVACC TXRDY RXRDY TXCOMP
Access
R R R R R R R
Reset 0 0 0 0 0 0 0
Bit 21 – SMBHHM SMBus Host Header Address Match Interrupt Mask
Bit 20 – SMBDAM SMBus Default Address Match Interrupt Mask
Bit 19 – PECERR PEC Error Interrupt Mask
Bit 18 – T
OUT Timeout Error Interrupt Mask
Bit 16 – MCACK Master Code Acknowledge Interrupt Mask
Bit 11 – EOSACC End Of Slave Access Interrupt Mask
Bit 10 – SCL_WS Clock Wait State Interrupt Mask
Bit 9 – ARBLST Arbitration Lost Interrupt Mask
Bit 8 – NACK Not Acknowledge Interrupt Mask
Bit 7 – UNRE Underrun Error Interrupt Mask
Bit 6 – OVRE Overrun Error Interrupt Mask
Bit 5 – GACC General Call Access Interrupt Mask
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1105