Datasheet
Bit 4 – SVACC Slave Access Interrupt Disable
Bit 2 – TXRDY T
ransmit Holding Register Ready Interrupt Disable
Bit 1 – RXRDY Receive Holding Register Ready Interrupt Disable
Bit 0 – TXCOMP Transmission Completed Interrupt Disable
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1104