Datasheet

43.7.10 TWIHS Interrupt Disable Register
Name: TWIHS_IDR
Offset: 0x28
Reset: –
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Disables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SMBHHM SMBDAM PECERR TOUT MCACK
Access
W W W W W
Reset – – – – –
Bit 15 14 13 12 11 10 9 8
EOSACC SCL_WS ARBLST NACK
Access
W W W W
Reset – – – –
Bit 7 6 5 4 3 2 1 0
UNRE OVRE GACC SVACC TXRDY RXRDY TXCOMP
Access
W W W W W W W
Reset – – – – – – –
Bit 21 – SMBHHM SMBus Host Header Address Match Interrupt Disable
Bit 20 – SMBDAM SMBus Default Address Match Interrupt Disable
Bit 19 – PECERR PEC Error Interrupt Disable
Bit 18 – T
OUT Timeout Error Interrupt Disable
Bit 16 – MCACK Master Code Acknowledge Interrupt Disable
Bit 11 – EOSACC End Of Slave Access Interrupt Disable
Bit 10 – SCL_WS Clock Wait State Interrupt Disable
Bit 9 – ARBLST Arbitration Lost Interrupt Disable
Bit 8 – NACK Not Acknowledge Interrupt Disable
Bit 7 – UNRE Underrun Error Interrupt Disable
Bit 6 – OVRE Overrun Error Interrupt Disable
Bit 5 – GACC General Call Access Interrupt Disable
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1103