Datasheet

43.7.9 TWIHS Interrupt Enable Register
Name: TWIHS_IER
Offset: 0x24
Reset: –
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Enables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SMBHHM SMBDAM PECERR TOUT MCACK
Access
W W W W W
Reset – – – – –
Bit 15 14 13 12 11 10 9 8
EOSACC SCL_WS ARBLST NACK
Access
W W W W
Reset – – – –
Bit 7 6 5 4 3 2 1 0
UNRE OVRE GACC SVACC TXRDY RXRDY TXCOMP
Access
W W W W W W W
Reset – – – – – – –
Bit 21 – SMBHHM SMBus Host Header Address Match Interrupt Enable
Bit 20 – SMBDAM SMBus Default Address Match Interrupt Enable
Bit 19 – PECERR PEC Error Interrupt Enable
Bit 18 – T
OUT Timeout Error Interrupt Enable
Bit 16 – MCACK Master Code Acknowledge Interrupt Enable
Bit 11 – EOSACC End Of Slave Access Interrupt Enable
Bit 10 – SCL_WS Clock Wait State Interrupt Enable
Bit 9 – ARBLST Arbitration Lost Interrupt Enable
Bit 8 – NACK Not Acknowledge Interrupt Enable
Bit 7 – UNRE Underrun Error Interrupt Enable
Bit 6 – OVRE Overrun Error Interrupt Enable
Bit 5 – GACC General Call Access Interrupt Enable
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1101