Datasheet

43.7.7 TWIHS SMBus Timing Register
Name: TWIHS_SMBTR
Offset: 0x38
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the TWIHS W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
THMAX[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
TLOWM[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TLOWS[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PRESC[3:0]
Access
Reset 0 0 0 0
Bits 31:24 – THMAX[7:0] Clock High Maximum Cycles
Clock cycles in clock high maximum count. Prescaled by PRESC. Used for bus free detection. Used to time
THIGH:MAX.
Bits 23:16 – TLOWM[7:0] Master Clock Stretch Maximum Cycles
Value Description
0
TLOW:MEXT timeout check disabled.
1–255
Clock cycles in master maximum clock stretch count. Prescaled by PRESC. Used to time
TLOW
:MEXT.
Bits 15:8 – TLOWS[7:0] Slave Clock Stretch Maximum Cycles
Value Description
0
TLOW:SEXT timeout check disabled.
1–255
Clock cycles in slave maximum clock stretch count. Prescaled by PRESC. Used to time TLOW:SEXT.
Bits 3:0 – PRESC[3:0] SMBus Clock Prescaler
Used to specify how to prescale the TLOWS, TLOWM and THMAX counters in SMBTR. Counters are prescaled
according to the following formula:

Prescaled
=

peripheralclock
2
PRESC + 1
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1099