Datasheet

43.7.6 TWIHS Status Register
Name: TWIHS_SR
Offset: 0x20
Reset: 0x03000009
Property: Read-only
Bit 31 30 29 28 27 26 25 24
SDA SCL
Access
R R
Reset 1 1
Bit 23 22 21 20 19 18 17 16
SMBHHM SMBDAM PECERR TOUT MCACK
Access
R R R R R
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
EOSACC SCLWS ARBLST NACK
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
UNRE OVRE GACC SVACC SVREAD TXRDY RXRDY TXCOMP
Access
R R R R R R R R
Reset 0 0 0 0 1 0 0 1
Bit 25 – SDA SDA Line V
alue
Value Description
0
SDA line sampled value is ‘0’.
1
SDA line sampled value is ‘1’.
Bit 24 – SCL SCL Line V
alue
Value Description
0
SCL line sampled value is ‘0’.
1
SCL line sampled value is ‘1.’
Bit 21 – SMBHHM SMBus Host Header Address Match (cleared on read)
Value Description
0
No SMBus Host Header Address received since the last read of TWIHS_SR.
1
An SMBus Host Header Address was received since the last read of TWIHS_SR.
Bit 20 – SMBDAM SMBus Default Address Match (cleared on read)
Value Description
0
No SMBus Default Address received since the last read of TWIHS_SR.
1
An SMBus Default Address was received since the last read of TWIHS_SR.
Bit 19 – PECERR PEC Error (cleared on read)
Value Description
0
No SMBus PEC error occurred since the last read of TWIHS_SR.
1
An SMBus PEC error occurred since the last read of TWIHS_SR.
Bit 18 – TOUT T
imeout Error (cleared on read)
Value Description
0
No SMBus timeout occurred since the last read of TWIHS_SR.
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1095