Datasheet

43.7.2 TWIHS Master Mode Register
Name: TWIHS_MMR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
DADR[6:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
MREAD IADRSZ[1:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
Access
Reset
Bits 22:16 – DADR[6:0] Device Address
The device address is used to access slave devices in Read or W
rite mode. These bits are only used in Master
mode.
Bit 12 – MREAD Master Read Direction
Value Description
0
Master write direction.
1
Master read direction.
Bits 9:8 – IADRSZ[1:0] Internal Device Address Size
Value Name Description
0
NONE No internal device address
1
1_BYTE One-byte internal device address
2
2_BYTE Two-byte internal device address
3
3_BYTE Three-byte internal device address
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1090