Datasheet

Note: When slave clock stretching is disabled, the TWIHS_RHR must always be read before receiving the next data
(MASTER write frame). It is strongly recommended to use either the polling method on the RXRDY flag in
TWIHS_SR, or the DMA. If the receive is managed by an interrupt, the TWIHS interrupt priority must be set to the
right level and its latency minimized to avoid receive overrun.
Note: When slave clock stretching is disabled, the TWIHS_THR must be filled with the first data to send before the
beginning of the frame (MASTER read frame). It is strongly recommended to use either the polling method on the
TXRDY flag in TWIHS_SR, or the DMA. If the transmit is managed by an interrupt, the TWIHS interrupt priority must
be set to the right level and its latency minimized to avoid transmit underrun.
43.6.5.7.1 Read/Write Operation
A TWIHS high-speed frame always begins with the following sequence:
1.
START condition (S)
2. Master Code (0000 1XXX)
3. Not-acknowledge (NACK)
When the TWIHS is programmed in Slave mode and TWIHS High-speed mode is activated, master code matching is
activated and internal timings are set to match the TWIHS High-speed mode requirements.
Figure 43-38. High-Speed Mode Read/Write
NA SADR R/WS MASTER CODE DATA A/NA P
Sr A
NA SADR R/WS MASTER CODE DATA A/NA Sr
Sr A
SADR
P
F/S Mode
F/S Mode HS Mode
HS Mode
F/S Mode
F/S Mode
43.6.5.7.2 Usage
TWIHS High-speed mode usage is the same as the standard TWIHS (See Read/W
rite Flowcharts).
43.6.5.8 Asynchronous Partial Wakeup (SleepWalking)
The TWIHS includes an asynchronous start condition detector. It is capable of waking the device up from a Sleep
mode upon an address match (and optionally an additional data match), including Sleep modes where the TWIHS
peripheral clock is stopped.
After detecting the START condition on the bus, the TWIHS stretches TWCK until the TWIHS peripheral clock has
started. The time required for starting the TWIHS depends on which Sleep mode the device is in. After the TWIHS
peripheral clock has started, the TWIHS releases its TWCK stretching and receives one byte of data (slave address)
on the bus. At this time, only a limited part of the device, including the TWIHS module, receives a clock, thus saving
power. If the address phase causes a TWIHS address match (and, optionally, if the first data byte causes data match
as well), the entire device is woken up and normal TWIHS address matching actions are performed. Normal TWIHS
transfer then follows. If the TWIHS is not addressed (or if the optional data match fails), the TWIHS peripheral clock is
automatically stopped and the device returns to its original Sleep mode.
The TWIHS has the capability to match on more than one address. The SADR1EN, SADR2EN and SADR3EN bits in
TWIHS_SMR enable address matching on additional addresses which can be configured through SADR1, SADR2
and SADR3 fields in the TWIHS_SWMR. The SleepWalking matching process can be extended to the first received
data byte if TWIHS_SMR.DATAMEN is set and, in this case, a complete matching includes address matching and
first received data matching. TWIHS_SWMR.DATAM configures the data to match on the first received byte.
When the system is in Active mode and the TWIHS enters Asynchronous Partial Wakeup mode, the flag SVACC
must be programmed as the unique source of the TWIHS interrupt and the data match comparison must be disabled.
When the system exits Wait mode as the result of a matching condition, the SVACC flag is used to determine if the
TWIHS is the source of exit.
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1078