Datasheet

43.6.5.4.5 Reversal after a Repeated Start
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
The figure below describes the REPEA
TED START and the reversal from Read mode to Write mode.
Figure 43-36. Repeated Start and Reversal from Read Mode to Write Mode
S SADR R ADATA0A DATA1
SADRSr
NA
W A DATA2 A DATA3 A P
Cleared after read
DA
TA0 DATA1
DATA2 DATA3
SVACC
SVREAD
TWD
TWIHS_THR
TWIHS_RHR
EOSACC
TXRDY
RXRDY
TXCOMP
As soon as a START is detected
Note: TXCOMP is only set at the end of the transmission. This is because after the REPEATED START, SADR is
detected again.
Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command. The figure below
describes the REPEA
TED START and the reversal from Write mode to Read mode.
Figure 43-37. Repeated Start and Reversal from Write Mode to Read Mode
S SADR W ADATA0A DATA1
SADRSr
A
R A DATA2 A DATA3 NA P
Cleared after read
DA
TA0
DATA2 DATA3
DATA1
TXCOMP
TXRDY
RXRDY
As soon as a START is detected
Read TWIHS_RHR
SVACC
SVREAD
TWD
TWIHS_RHR
TWIHS_THR
EOSACC
Note:
1.
In this case, if TWIHS_THR has not been written at the end of the read command, the clock is automatically
stretched before the ACK.
2. TXCOMP is only set at the end of the transmission. This is because after the REPEATED START, SADR is
detected again.
43.6.5.5 Using the DMA Controller (DMAC) in Slave Mode
The use of the DMAC significantly reduces the CPU load.
43.6.5.5.1 Data Transmit with the DMA in Slave Mode
The following procedure shows an example to transmit data with DMA.
1.
Initialize the transmit DMA (memory pointers, transfer size, etc).
2. Configure the Slave mode.
3. Enable the DMA.
4. Wait for the DMA status flag indicating that the buffer transfer is complete.
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1076