Datasheet

Figure 43-34. Clock Stretching in Read Mode
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWIHS_THR
TXCOMP
The data is memorized in TWIHS_THR until a new value is written
TWIHS_THR is transmitted to the internal shifter
Ack or Nack from the master
DA
TA0DATA0 DATA2
1
2
1
CLOCK is tied low by the TWIHS
as long as
THR is empty
S
SADR
S
R DATA0A
A
DATA1
A DATA2 NA S
XXXXXXX
2
Write THR
As soon as a START is detected
Note:
1.
TXRDY is reset when data has been written in TWIHS_THR to the internal shifter and set when this data has
been acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address
different from SADR.
3. SCLWS is automatically set when the clock stretching mechanism is started.
Clock Stretching in Write Mode
The clock is tied low if the internal shifter and TWIHS_RHR is full. If a STOP or REPEATED_START condition was
not detected, it is tied low until TWIHS_RHR is read.
The figure below describes the clock stretching in Write mode.
Figure 43-35. Clock Stretching in Write Mode
Rd DATA0
Rd DATA1
Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA1
DATA2
SCL is stretched after the acknowledge of DATA1
As soon as a START is detected
TWCK
TWD
TWIHS_RHR
CL
OCK is tied low by the TWIHS as long as RHR is full
DATA0 is not read in the RHR
ADRS SADR W ADATA0A
A
DATA2DATA1 S
NA
Note:
1.
At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address
different from SADR.
2. SCLWS is automatically set when the clock stretching mechanism is started and automatically reset when the
mechanism is finished.
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1075