Datasheet

Figure 43-30. Multimaster Flowchart
Program Slave mode:
SADR + MSDIS + SVEN
SVACC = 1 ?
TXCOMP = 1 ?
GACC = 1 ?
Decoding of the
programming sequence
Prog seq
OK ?
Change SADR
SVREAD = 1 ?
Read Status Register
RXRDY= 1 ?
Read TWIHS_RHR
TXRDY= 1 ?
EOSACC = 1 ?
W
rite in TWIHS_THR
Need to perform
a master access ?
Program Master mode
DADR + SVDIS + MSEN + CLK + R / W
Read Status Register
ARBLST = 1 ?
MREAD = 1 ?
TXRDY= 0 ?
Write in TWIHS_THR
Data to send ?
RXRDY= 0 ?
Read TWIHS_RHR
Data to read?
Read Status Register
TXCOMP = 0 ?
GENERAL CALL TREATMENT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Stop Transfer
TWIHS_CR = STOP
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
START
43.6.5 Slave Mode
43.6.5.1 Definition
Slave mode is defined as a mode where the device receives the clock and the address from another device called
the master
.
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1071