Datasheet

Figure 43-26. TWIHS Read Operation with Multiple Data Bytes + Write Operation with Multiple Data Bytes (Sr)
Internal address size = 0?
Start the transfer
TWIHS_CR = START
Start the transfer (Sr)
TWIHS_CR = START
Read Status register
RXRDY = 1?
Last data to read
but one?
Read status register
TXCOMP = 1?
END
Set the internal address
TWIHS_IADR = address
Yes
Yes
Yes
No
Yes
Read Receive Holding register (TWIHS_RHR)
No
Set the Control register:
- Master enable
TWIHS_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
BEGIN
Set TWIHS clock
(CLDIV, CHDIV, CKDIV) in TWIHS_CWGR
(Needed only once)
No
No
Read Status register
RXRDY = 1?
Yes
Read Receive Holding register (TWIHS_RHR)
No
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
-TWIHS_IADR = address (if Internal address size = 0)
- Transfer direction bit
Read ==> bit MREAD = 0
Read Status register
TXRDY = 1?
Data to send ?
TWIHS_THR = data to send
Stop the transfer
TWIHS_CR = STOP
Yes
No
Yes
Set the next transfer
parameters and
send the repeated start
command
Read the last byte
of the first read transfer
No
SAM E70/S70/V70/V71 Family
T
wo-wire Interface (TWIHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1067