Datasheet

Figure 43-22. TWIHS Read Operation with Single Data Byte and Internal Address

Set the Control register:

- Master enable

TWIHS_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Internal address size (IADRSZ)

- Transfer direction bit

Read ==> bit MREAD = 1

Read Status register

TXCOMP = 1?

END

BEGIN

Yes

Set TWIHS clock

(CLDIV, CHDIV, CKDIV) in TWIHS_CWGR

(Needed only once)

Yes

Set the internal address

TWIHS_IADR = address

Start the transfer

TWIHS_CR = START | STOP

Read Status register

RXRDY = 1?

Read Receive Holding register

SAM E70/S70/V70/V71 Family

wo-wire Interface (TWIHS)

echnology Inc.

Datasheet

DS60001527D-page 1063