Datasheet

42.7.8 QSPI Interrupt Mask Register
Name: QSPI_IMR
Offset: 0x1C
Reset: 0x00000000
Property: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
INSTRE CSS CSR
Access
R R R
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
OVRES TXEMPTY TDRE RDRF
Access
R R R R
Reset 0 0 0 0
Bit 10 – INSTRE Instruction End Interrupt Mask
Bit 9 – CSS Chip Select Status Interrupt Mask
Bit 8 – CSR Chip Select Rise Interrupt Mask
Bit 3 – OVRES Overrun Error Interrupt Mask
Bit 2 – TXEMPTY
Transmission Registers Empty Mask
Bit 1 – TDRE Transmit Data Register Empty Interrupt Mask
Bit 0 – RDRF Receive Data Register Full Interrupt Mask
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
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echnology Inc.
Datasheet
DS60001527D-page 1034