Datasheet

42.7.5 QSPI Status Register
Name: QSPI_SR
Offset: 0x10
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
QSPIENS
Access
R
Reset 0
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
INSTRE CSS CSR
Access
R R R
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
OVRES TXEMPTY TDRE RDRF
Access
R R R R
Reset 0 0 0 0
Bit 24 – QSPIENS QSPI Enable Status
Value Description
0
QSPI is disabled.
1
QSPI is enabled.
Bit 10 – INSTRE Instruction End Status (cleared on read)
Value Description
0
No instruction end has been detected since the last read of QSPI_SR.
1
At least one instruction end has been detected since the last read of QSPI_SR.
Bit 9 – CSS Chip Select Status
Value Description
0
The chip select is asserted.
1
The chip select is not asserted.
Bit 8 – CSR Chip Select Rise (cleared on read)
Value Description
0
No chip select rise has been detected since the last read of QSPI_SR.
1
At least one chip select rise has been detected since the last read of QSPI_SR.
Bit 3 – OVRES Overrun Error Status (cleared on read)
An overrun occurs when QSPI_RDR is loaded at least twice from the serializer since the last read of the QSPI_RDR.
Value Description
0
No overrun has been detected since the last read of QSPI_SR.
1
At least one overrun error has occurred since the last read of QSPI_SR.
Bit 2 – TXEMPTY T
ransmission Registers Empty (cleared by writing QSPI_TDR)
Value Description
0
As soon as data is written in QSPI_TDR.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1030