Datasheet

42.7.2 QSPI Mode Register
Name: QSPI_MR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write
This register can only be written if bit WPEN is cleared in the QSPI W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
DLYCS[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DLYBCT[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
NBBITS[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CSMODE[1:0] WDRBT LLB SMM
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 31:24 – DLYCS[7:0] Minimum Inactive QCS Delay
This field defines the minimum delay between the deactivation and the activation of QCS. The DL
YCS time
guarantees the slave minimum deselect time.
If DLYCS written to ‘0’, one peripheral clock period is inserted by default.
Otherwise, the following equation determines the delay:
DLYCS = Minimum inactive × f
peripheral clock
Bits 23:16 – DLYBCT[7:0] Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip
select. The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT is written to ‘0’, no delay between consecutive transfers is inserted and the clock keeps its duty cycle
over the character transfers. In Serial Memory mode (SMM = 1), DLYBCT must be written to ‘0’ and no delay is
inserted.
Otherwise, the following equation determines the delay:
DLYBCT = (Delay Between Consecutive Transfers × f
peripheral clock
) / 32
Bits 11:8 – NBBITS[3:0] Number Of Bits Per Transfer
Value Name Description
0
8_BIT 8 bits for transfer
8
16_BIT 16 bits for transfer
Bits 5:4 – CSMODE[1:0] Chip Select Mode
The CSMODE field determines how the chip select is deasserted
Note: This field is forced to LASTXFER when SMM is written to ‘1’.
Value Name Description
0
NOT_RELOADED The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the
end of the current transfer
.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1026