Datasheet

19.4.2 Bus Matrix Slave Configuration Registers
Name: MATRIX_SCFGx
Offset: 0x40 + x*0x04 [x=0..8]
Reset: 0x000001FF
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SLOT_CYCLE[8:7]
Access
R/W R/W
Reset 0 1
Bit 7 6 5 4 3 2 1 0
SLOT_CYCLE[6:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1
Bits 21:18 – FIXED_DEFMSTR[3:0] Fixed Default Master
Number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master
which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
Bits 17:16 – DEFMSTR_TYPE[1:0]
Default Master Type
Value Name Description
0
NONE No Default Master—At the end of the current slave access, if no other master request is
pending, the slave is disconnected from all masters.
This results in a one clock cycle latency for the first access of a burst transfer or for a single
access.
1
LAST Last Default Master—At the end of the current slave access, if no other master request is
pending, the slave stays connected to the last master having accessed it.
This results in not having one clock cycle latency when the last master tries to access the
slave again.
2
FIXED Fixed Default Master—At the end of the current slave access, if no other master request is
pending, the slave connects to the fixed master the number that has been written in the
FIXED_DEFMSTR field.
This results in not having one clock cycle latency when the fixed master tries to access the
slave again.
Bits 9:1 – SLOT_CYCLE[8:0] Maximum Bus Grant Duration for Masters
When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place to let
another master access this slave. If another master is requesting the slave bus, then the current master burst is
broken.
If SLOT_CYCLE = 0, the slot cycle limit feature is disabled and bursts always complete unless broken according to
the ULBT
.
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 102