Datasheet

Figure 42-13. Instruction Transmission Waveform 3
QCS
QSCK
MOSI / QIO0
Instruction 20h
Write QSPI_IFR
Address
A23 A22 A21 A20 A3 A2 A1 A0
QSPI_SR.INSTRE
Write QSPI_IAR
Example 4:
Instruction in Single-bit SPI, without address, without option, with data write in Single-bit SPI.
Command: SET BURST (77h)
•
Write 0x0000_0077 in QSPI_ICR.
• Write 0x0000_2090 in QSPI_IFR.
• Read QSPI_IFR (dummy read) to synchronize system bus accesses.
• Write data in the system bus memory space (0x80000000).
The address of system bus write accesses is not used.
• Write a ‘1’ to QSPI_CR.LASTXFR.
• Wait for QSPI_SR.INSTRE to rise.
Figure 42-14. Instruction Transmission Waveform 4
QCS
QSCK
MOSI / QIO0
Instruction 77h
Write QSPI_IFR
Data
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
QSPI_SR.INSTRE
Write AHB
Set QSPI_CR.LASTXFR
Example 5:
Instruction in Single-bit SPI, with address in Dual SPI, without option, with data write in Dual SPI.
Command: BYTE/P
AGE PROGRAM (02h)
• Write 0x0000_0002 in QSPI_ICR.
• Write 0x0000_30B3 in QSPI_IFR.
• Read QSPI_IFR (dummy read) to synchronize system bus accesses.
• Write data in the QSPI system bus memory space (0x80000000).
The address of the first system bus write access is sent in the instruction frame.
The address of the next system bus write accesses is not used.
• Write a ‘1’ to QSPI_CR.LASTXFR.
• Wait for QSPI_SR.INSTRE to rise.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1018