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1011

42.6.5.3 Read Memory Transfer

The user can access the data of the serial memory by sending an instruction with QSPI_IFR.DATAEN = 1 and

QSPI_IFR.TFR

TYP = 1.

In this mode, the QSPI is able to read data at random address into the serial Flash memory, allowing the CPU to

execute code directly from it (XIP execute-in-place).

In order to fetch data, the user must first configure the instruction frame by writing the QSPI_IFR. Then data can be

read at any address in the QSPI address space mapping. The address of the system bus read accesses match the

address of the data inside the serial Flash memory.

When Fetch mode is enabled, several instruction frames can be sent before writing QSPI_CR.LASTXFR. Each time

the system bus read accesses become nonsequential (addresses are not consecutive), a new instruction frame is

sent with the corresponding address.

42.6.5.4 Continuous Read Mode

The QSPI is compatible with the Continuous Read mode which is implemented in some serial Flash memories.

In Continuous Read mode, the instruction overhead is reduced by excluding the instruction code from the instruction

frame. When the Continuous Read mode is activated in a serial Flash memory by a specific option code, the

instruction code is stored in the memory

. For the next instruction frames, the instruction code is not required as the

memory uses the stored one.

In the QSPI, Continuous Read mode is used when reading data from the memory (QSPI_IFR.TFRTYP = 1). The

addresses of the system bus read accesses are often nonsequential and this leads to many instruction frames that

have the same instruction code. By disabling the send of the instruction code, the Continuous Read mode reduces

the access time of the data.

To be functional, this mode must be enabled in both the QSPI and the serial Flash memory. The Continuous Read

mode is enabled in the QSPI by writing CRM to ‘1’ in the QSPI_IFR (TFRTYP must equal 1). The Continuous Read

mode is enabled in the serial Flash memory by sending a specific option code.

CAUTION

If the Continuous Read mode is not supported by the serial Flash memory or disabled, CRM bit must not

be written to ‘1’, otherwise data read out of the serial Flash memory is unpredictable.

Figure 42-10. Continuous Read Mode

QCS

QSCK

QIO0

Instruction

Data

QIO1

QIO2

QIO3

Option

to activate the

Continuous Read Mode

in the serial flash memory

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

Address

Instruction code is not

required

Option

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

Data

Address

42.6.5.5 Instruction Frame Transmission Examples

All waveforms in the following examples describe SPI transfers in SPI Clock mode 0 (QSPI_SCR.CPOL = 0 and

QSPI_SCR.CPHA = 0; see section Serial Clock Phase and Polarity).

All system bus accesses described below refer to the system bus address phase. System bus wait cycles and

system bus data phases are not shown.

Example 1:

Instruction in Single-bit SPI, without address, without option, without data.

Command: CHIP ERASE (C7h).

•

Write 0x0000_00C7 in QSPI_ICR.

• Write 0x0000_0010 in QSPI_IFR.

SAM E70/S70/V70/V71 Family

Quad Serial Peripheral Interface (QSPI)

echnology Inc.

Datasheet

DS60001527D-page 1016