Datasheet

Figure 42-9. Instruction Transmission Flow Diagram
Configure and send insruction
frame by writing QSPI_IFR
Instruction frame
with data
?
Instruction frame
with address
?
Read memory
transfer
(TFRTYP = 1)
?
Read DATA in the QSPI AHB
memory space.
If accesses are not sequential
a new instruction is sent
automatically.
Read/Write DATA in the QSPI
AHB memory space.
The address of the first access
is sent after the instruction
code.
Yes
No
Read/Write DATA in the QSPI
AHB memory space.
Address of accesses are not
used by the QSPI.
No
Yes
Yes
No
Write QSPI_CR.LASTXFR to 1
when all data have been
transferred.
Wait for flag QSPI_SR.INSTRE
to rise by polling or interrupt.
START
END
Read QSPI_IFR (dummy read)
to synchronize APB and AHB
accesses
Write the address in QSPI_IAR
Instruction frame
with address
but no data
?
Yes
No
Write the instruction code
and/or the option code
in QSPI_ICR
Instruction frame
with instruction code and/or
option code
?
Yes
No
Depending on CSMODE configuration
wait for flag QSPI_SR.CSR
to rise by polling or interrupt.
Read QSPI_SR (dummy read)
to clear QSPI_SR.INSTRE and
QSPI_SR.CSR.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1015