Datasheet
42.6.5 QSPI Serial Memory Mode
In Serial Memory mode, the QSPI acts as a serial Flash memory controller. The QSPI can be used to read data from
the serial Flash memory allowing the CPU to execute code from it (XIP execute in place). The QSPI can also be used
to control the serial Flash memory (Program, Erase, Lock, etc.) by sending specific commands. In this mode, the
QSPI is compatible with single-bit SPI, Dual SPI and Quad SPI protocols.
T
o activate this mode, QSPI_MR.SMM must be written to ‘1’.
In Serial Memory mode, data is transferred only by writing or reading the QSPI memory space (0x80000000).
42.6.5.1 Instruction Frame
In order to control serial Flash memories, the QSPI is able to send instructions via the SPI bus (ex: READ,
PROGRAM, ERASE, LOCK, etc.). Because the instruction set implemented in serial Flash memories is memory
vendor-dependent, the QSPI includes a complete Instruction Frame register (QSPI_IFR), which makes it very flexible
and compatible with all serial Flash memories.
An instruction frame includes:
• An instruction code (size: 8 bits). The instruction is optional in some cases (see section Continuous Read
mode).
• An address (size: 24 bits or 32 bits). The address is optional but is required by instructions such as READ,
PROGRAM, ERASE, LOCK. By default the address is 24 bits long, but it can be 32 bits long to support serial
Flash memories larger than 128 Mbits (16 Mbytes).
• An option code (size: 1/2/4/8 bits). The option code is not required, but it is useful to activate the XIP mode or
the Continuous Read mode (see section Continuous Read mode) for READ instructions, in some serial Flash
memory devices. These modes improve the data read latency.
• Dummy cycles. Dummy cycles are optional but required by some READ instructions.
• Data bytes are optional. Data bytes are present for data transfer instructions such as READ or PROGRAM.
The instruction code, the address/option and the data can be sent with Single-bit SPI, Dual SPI or Quad SPI
protocols.
Figure 42-8. Instruction Frame
QCS
QSCK
QIO0
Instruction EBh
Data
QIO1
QIO2
QIO3
Dummy cycles
Address Option
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O7
O6
O5
O4
O3
O2
O1
O0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
42.6.5.2 Instruction Frame Transmission
To send an instruction frame, the user must first configure the address to send by writing the field ADDR in the
Instruction Address register (QSPI_IAR). This step is required if the instruction frame includes an address and no
data. When data is present, the address of the instruction is defined by the address of the data accesses in the QSPI
memory space, not by QSPI_IAR.
If the instruction frame includes the instruction code and/or the option code, the user must configure the instruction
code and/or the option code to send by writing the fields
INST and OPT in the Instruction Code register (QSPI_ICR).
Then, the user must write QSPI_IFR to configure the instruction frame depending on which instruction must be sent.
If the instruction frame does not include data, writing in this register triggers the send of the instruction frame in the
QSPI. If the instruction frame includes data, the send of the instruction frame is triggered by the first data access in
the QSPI memory space.
The instruction frame is configured by the following bits and fields of QSPI_IFR:
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1013