Datasheet

Figure 42-7. Status Register Flags Behavior
6
QSCK
MOSI
(from master)
MISO
(from slave)
QCS
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
RDRF
TDRE
TXEMPTY
Write in
QSPI_TDR
QSPI_RDR read
shift register empty
42.6.4.4 Peripheral Deselection without DMA
During a transfer of more than one data on a Chip Select without the DMA, the QSPI_TDR is loaded by the processor
and the flag TDRE rises as soon as the content of the QSPI_TDR is transferred into the internal shift register
. When
this flag is detected high, the QSPI_TDR can be reloaded. If this reload by the processor occurs before the end of the
current transfer, the Chip Select is not deasserted between the two transfers. Depending on the application software
handling the QSPI_SR flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor
may not reload the QSPI_TDR in time to keep the chip select active (low). A null Delay Between Consecutive
Transfer (DLYBCT) value in the QSPI_MR gives even less time for the processor to reload the QSPI_TDR. With
some SPI slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers may lead
to communication errors.
To facilitate interfacing with such devices, QSPI_MR.CSMODE may be configured to ‘1’. This allows the chip select
lines to remain in their current state (low = active) until the end of transfer is indicated by the Last Transfer
(LASTXFER) bit in the Control register (QSPI_CR). Even if the QSPI_TDR is not reloaded, the chip select remains
active. To have the chip select line rise at the end of the last data transfer, QSPI_CR.LASTXFER must be written to
‘1’ at the same time or after writing the last data to transmit into the QSPI_TDR.
42.6.4.5 Peripheral Deselection with DMA
When the DMA Controller is used, the Chip Select line remains low during the transfer since the TDRE flag is
managed by the DMA itself. Reloading the QSPI_TDR by the DMA is done as soon as the TDRE flag is set. In this
case, writing QSPI_MR.CSMODE to ‘1’ may not be needed. However, when other DMA channels connected to other
peripherals are also in use, the QSPI DMA could be delayed by another DMA with a higher priority on the bus.
Having DMA buffers in slower memories like Flash memory or SDRAM compared to fast internal SRAM, may
lengthen the reload time of the QSPI_TDR by the DMA as well. This means that the QSPI_TDR might not be
reloaded in time to keep the chip select line low. In this case, the chip select line may toggle between data transfer
and according to some SPI Slave devices, the communication might get lost. It may be necessary to configure
QSPI_MR.CSMODE to ‘1’.
When QSPI_MR.CSMODE is configured to ‘0’, the QCS does not rise in all cases between two transfers on the same
peripheral. During a transfer on a Chip Select, the flag TDRE rises as soon as the content of the QSPI_TDR is
transferred into the internal shifter. When this flag is detected, the QSPI_TDR can be reloaded. If this reload occurs
before the end of the current transfer, the Chip Select is not deasserted between the two transfers. This might lead to
difficulties for interfacing with some serial peripherals requiring the chip select to be deasserted after each transfer. To
facilitate interfacing with such devices, the QSPI_MR may be configured with QSPI_MR.CSMODE at ‘2’.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1012