Datasheet

42.6.4.3 SPI Mode Flow Diagram
Figure 42-6. SPI Mode Flow Diagram
QSPI Enable
1
NPCS = 0
Delay DLYBS
Serializer = QSPI_TDR(TD)
TDRE = 1
Data Transfer
QSPI_RDR(RD) = Serializer
RDRF = 1
TDRE ?
NPCS = 1
Delay DLYCS
Delay DLYBCT
0
TDRE ?
1
0
The figure below shows Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and
T
ransmission Register Empty (TXEMPTY) status flags behavior within the QSPI_SR during an 8-bit data transfer in
Fixed mode, without DMA.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1011