Datasheet

Figure 42-2. QSPI Transfer Format (QSPI_SCR.CPHA = 0, 8 bits per transfer)
6
*
QSCK
(CPOL = 0)
QSCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
QCS
(to slave)
QSCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined, but normally MSB of previous character received.
1 2345 786
Figure 42-3. QSPI Transfer Format (QSPI_SCR.CPHA = 1, 8 bits per transfer)
*
QSCK
(CPOL = 0)
QSCK
(CPOL = 1)
1 2345 7
MOSI
(from master)
MISO
(from slave)
QCS
(to slave)
QSCK cycle (for reference)
8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
* Not defined but normally LSB of previous character transmitted.
2
2
6
42.6.3 Transfer Delays
The figure below shows several consecutive transfers while the chip select is active. Three delays can be
programmed to modify the transfer waveforms:
•
The delay between the deactivation and the activation of QCS, programmed by writing QSPI_MR.DLYCS.
Allows to adjust the minimum time of QCS at high level.
• The delay before QSCK, programmed by writing QSPI_SR.DLYBS. Allows the start of QSCK to be delayed after
the chip select has been asserted.
• The delay between consecutive transfers, programmed by writing QSPI_MR.DLYBCT. Allows insertion of a
delay between two consecutive transfers. In Serial Memory mode, this delay is not programmable and DLYBCT
is ignored. In this mode, DLYBCT must be written to ‘0’.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1008