Datasheet

42.5.3 Interrupt Sources
The QSPI has an interrupt line connected to the Interrupt Controller. Handling the QSPI interrupt requires
programming the interrupt controller before configuring the QSPI.
42.5.4 Direct Memory Access Controller (DMA)
The QSPI can be used in conjunction with the Direct Memory Access Controller (DMA) in order to reduce processor
overhead. For a full description of the DMA, refer to the section “DMA Controller (XDMAC)”.
Note
: DMA write accesses must be 32-bit aligned. If a single byte is to be written in a 32-bit word, the rest of the
word must be filled with ones.
42.6 Functional Description
42.6.1 Serial Clock Baud Rate
The QSPI baud rate clock is generated by dividing the peripheral clock by a value between 1 and 256.
42.6.2 Serial Clock Phase and Polarity
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the QSPI Serial Clock register (QSPI_SCR). The CPHA bit in the QSPI_SCR programs the clock phase.
These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two
parameters has two possible states, resulting in four possible combinations that are incompatible with one another.
Thus, the interfaced slave must use the same parameter values to communicate.
The table below shows the four modes and corresponding parameter settings.
Table 42-2. QSPI Bus Clock Modes
QSPI Clock
Mode
QSPI_SCR.CPOL QSPI_SCR.CPHA Shift QSCK
Edge
Capture QSCK
Edge
QSCK Inactive
Level
0 0 0 Falling Rising Low
1 0 1 Rising Falling Low
2 1 0 Rising Falling High
3 1 1 Falling Rising High
The following figures show examples of data transfers.
SAM E70/S70/V70/V71 Family
Quad Serial Peripheral Interface (QSPI)
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1007